1) Field of the Invention
The present invention relates to a solid-state imaging apparatus and a control method of the solid-state imaging apparatus, in which complementary metal-oxide semiconductor (CMOS) image sensor is used.
2) Description of the Related Art
Solid-state imaging apparatuses using an active pixel sensor (APS) type of CMOS image sensor are well known (see Japanese Patent Laid-Open Publication No. 2003-169256). FIG. 1 is a block diagram of pixels and their peripheral parts in a conventional CMOS image sensor. A plurality of pixels P11 through Pmn are arranged in a matrix of m rows and n columns. The internal structure of all the pixels P11 through Pmn is identical. Driver D1 through Dm are connected, one to each row. Correlated double sampling (CDS) circuits C1 through Cn are connected, one to each column.
FIG. 2 is an equalization circuit diagram showing a magnified view of one row (the j-th row) shown in FIG. 1. Each of the pixels Pj1 and Pjn includes a photodiode 1, a transferring transistor 2, an amplifying transistor 3, a selecting transistor 4, and a resetting transistor 5. In the following explanation, the transmitting transistor 2, the amplifying transistor 3, the selecting transistor 4, and the resetting transistor 5 are assumed to be n-channel MOS transistors.
The transmitting transistor 2, the selecting transistor 4, and the resetting transistor 5 in each of the pixels Pj1 and Pjn belonging to a single row are respectively connected to a common transmission control signal line (hereinafter, “TG signal line”) 6, selection control signal line (hereinafter, “SEL signal line”) 7, and reset control signal line (hereinafter, “RST signal line”) 8. A driver Dj provided for the j-th row drives the TG signal line 6, the SEL signal line 7, and the RST signal line 8. The other rows have the same structure.
FIG. 3 is a timing chart showing an electrical change in the TG signal line 6, the SEL signal line 7, and the RST signal line 8 of the circuit structure shown in FIG. 2 during pixel signal reading. The potentials of the SEL signal line 7, the RST signal line 8, and the TG signal line 6 are low (Off) before time t1. At time t1, the potential of only the RST signal line 8 changes to high (On). At time t2, the potential of the RST signal line 8 changes to low (off) and the potential of the SEL signal line 7 changes to high (On). Next, at time t3 the TG signal line 6 changes to high (transmission). At time t4 the TG signal line 6 changes to low (Off). At t5 the SEL signal line 7 changes to low (off) and the circuit returns to the same state as before time t1.
The duration from t1 to t3 is a period for noise reading (noise read period). In the noise read period the voltage is impressed on the CDS circuits C1 through Cn via the resetting transistor 5, the amplifying transistor 3, and the selecting transistor 4. The CDS circuits C1 through Cn are reset when the voltage is impressed. The duration from t3 to t5 is a period for signal reading (signal read period). In the signal read period, the charge accumulated by the photoelectric conversion of the photodiode 1 is transmitted to the CDS circuits C1 through Cn through the transmitting transistor 2, the amplifying transistor 3, and the selecting transistor 4. The period after t5 is a period in which analog signals are converted to digital signals (Analog/Digital Conversion (ADC) period).
However, in the conventional solid-state imaging apparatus, the RST signal line 8, the SEL signal line 7, and the TG signal line 6 run parallel and in close proximity to one another. Consequently, as shown in FIG. 2, the TG signal line 6 changes to a state of capacitance coupling with the RST signal line 8, due to a parasitic capacitance 9 between the TG signal line 6 and the RST signal line 8. Similarly, the SEL signal line 7 also changes to a state of capacitance coupling with the TG signal line 6, due to a parasitic capacitance 10 between the SEL signal line 7 and the TG signal line 6. Consequently, when the potential in the RST signal line 8 and the SEL signal line 7 changes from low to high in the noise read period, the potential of the TG signal line 6 increases slightly, causing the charge accumulated in the photodiode 1 to leak marginally to the output end of the transmitting transistor 2.
FIG. 4 is a schematic diagram of an electrical change in the TG signal line 6 due to capacitance coupling. The impedance of the TG signal line 6 increases with the distance of the pixel from the driver Dj. As represented by reference numeral 11, the potential of the TG signal line 6 increases, thereby increasing the charge leak. Consequently, in the image produced by imaging, portions corresponding to the pixels further from the driver Dj tend to appear darker than the portions corresponding to the pixels closer to the driver Dj.
Conventionally, the impedance in the pixels further from the driver Dj in TG signal line 6 does not increase considerably when the number of pixels is around 300,000. Consequently, the amount of electrical change in the TG signal line 6 is also small, and hence, does not pose a problem. However, in recent years, the number of pixels has exceeded 1,000,000, and therefore, a long TG signal line 6 is required. Consequently, in the pixels further from the driver Dj, the impedance of the TG signal line 6 increases considerably, thereby increasing the potential in the TG signal line 6. Therefore, the charge leak from the photodiode 1 in the pixels that are further from the driver Dj, increases considerably. Thus, there is a large difference in the amount of charge leak in the pixels that are closer to the driver Dj and those that are further from the driver Dj, leading to a conspicuous difference in the resulting image.